Difference between revisions of "Fetch Decode Execute Cycle"
(→Execute Transfer Notation (LOAD)) |
(→Fetch Decode Execute Cycle) |
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| Line 6: | Line 6: | ||
[PC] → MAR | [PC] → MAR | ||
| − | [Memory] → MBR | + | [Memory]<sub>MAR</sub> → MBR |
[PC] + 1 → PC | [PC] + 1 → PC | ||
| Line 23: | Line 23: | ||
==Decode Transfer Notation== | ==Decode Transfer Notation== | ||
| − | [ | + | [CIR<sub>op-code</sub>] → CU |
===Explanation=== | ===Explanation=== | ||
The op code from the CIR is passed to the Control Unit | The op code from the CIR is passed to the Control Unit | ||
==Execute Transfer Notation (LOAD)== | ==Execute Transfer Notation (LOAD)== | ||
| − | [ | + | |
| − | [Memory] → MBR | + | [CIR<sub>operand</sub>] → MAR |
| + | [Memory]<sub>MAR</sub> → MBR | ||
[MBR] → A-reg | [MBR] → A-reg | ||
| + | |||
===Explanation=== | ===Explanation=== | ||
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register. | The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register. | ||
| Line 39: | Line 41: | ||
==Execute Transfer Notation (ADD)== | ==Execute Transfer Notation (ADD)== | ||
| + | |||
| + | [CIR<sub>operand</sub>] → MAR | ||
| + | [Memory]<sub>MAR</sub> → MBR | ||
| + | [MBR] + A-reg → A-reg | ||
===Explanation=== | ===Explanation=== | ||
| + | The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register. | ||
| + | |||
| + | The contents of the Memory address are fetched into the Memory Buffer Register. | ||
| + | |||
| + | Because it is a ADD the Memory Buffer Register is added to the current value of the A-reg (Accumulator), and then copied into the A-reg (Accumulator). | ||
==Execute Transfer Notation (STORE)== | ==Execute Transfer Notation (STORE)== | ||
| + | |||
| + | [CIR<sub>operand</sub>] → MAR | ||
| + | A-reg → MBR | ||
| + | [MBR] → Memory<sub>MAR</sub> | ||
===Explanation=== | ===Explanation=== | ||
Revision as of 09:30, 16 June 2017
Contents
Fetch Decode Execute Cycle
Fetch Transfer Notation
[PC] → MAR
[Memory]MAR → MBR
[PC] + 1 → PC
[MBR] → CIR
Explanation
The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.
The instruction at that address is then copied to the Memory Buffer Register.
Simultaneously, the contents of the Program Counter are incremented by 1.
The contents of the Memory Buffer Register are copied to the Current Instruction Register.
Decode Transfer Notation
[CIRop-code] → CU
Explanation
The op code from the CIR is passed to the Control Unit
Execute Transfer Notation (LOAD)
[CIRoperand] → MAR [Memory]MAR → MBR [MBR] → A-reg
Explanation
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.
The contents of the Memory address are fetched into the Memory Buffer Register.
Because it is a LOAD the Memory Buffer Register is copied into the A-reg (Accumulator).
Execute Transfer Notation (ADD)
[CIRoperand] → MAR [Memory]MAR → MBR [MBR] + A-reg → A-reg
Explanation
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.
The contents of the Memory address are fetched into the Memory Buffer Register.
Because it is a ADD the Memory Buffer Register is added to the current value of the A-reg (Accumulator), and then copied into the A-reg (Accumulator).
Execute Transfer Notation (STORE)
[CIRoperand] → MAR A-reg → MBR [MBR] → MemoryMAR
