Difference between revisions of "Fetch Decode Execute Cycle"

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(Execute Transfer Notation (LOAD))
(Fetch Decode Execute Cycle)
 
(8 intermediate revisions by the same user not shown)
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=Fetch Decode Execute Cycle=
 
=Fetch Decode Execute Cycle=
  
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<youtube>https://www.youtube.com/watch?v=yyHFI5juppA&index=118&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho</youtube>
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https://www.youtube.com/watch?v=yyHFI5juppA&index=118&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho
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===TRC Video===
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<youtube>https://www.youtube.com/watch?v=PGeNWlz2aaA</youtube>
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 +
https://www.youtube.com/watch?v=PGeNWlz2aaA
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=Fetch=
 
==Fetch Transfer Notation==
 
==Fetch Transfer Notation==
  
 
[PC] → MAR
 
[PC] → MAR
  
[Memory] → MBR
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[Memory<sub>mar</sub>] → MBR
  
 
[PC] + 1 → PC
 
[PC] + 1 → PC
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The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.  
 
The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.  
  
The instruction at that address is then copied to the Memory Buffer Register.
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The instruction at that address (stored in the Memory Address Register) is then copied to the Memory Buffer Register.
  
 
Simultaneously, the contents of the Program Counter are incremented by 1.  
 
Simultaneously, the contents of the Program Counter are incremented by 1.  
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The contents of the Memory Buffer Register are copied to the Current Instruction Register.
 
The contents of the Memory Buffer Register are copied to the Current Instruction Register.
  
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=Decode=
 
==Decode Transfer Notation==
 
==Decode Transfer Notation==
[CIRop-code] → CU
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[CIR<sub>op-code</sub>] → CU
 
===Explanation===
 
===Explanation===
 
The op code from the CIR is passed to the Control Unit
 
The op code from the CIR is passed to the Control Unit
  
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=Execute=
 
==Execute Transfer Notation (LOAD)==
 
==Execute Transfer Notation (LOAD)==
[CIRoperand] → MAR
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[Memory] → MBR
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[CIR<sub>operand</sub>] → MAR
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[Memory<sub>mar</sub>] → MBR
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[MBR] → A-reg
 
[MBR] → A-reg
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===Explanation===
 
===Explanation===
 
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.
 
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.
  
The contents of the Memory address are fetched into the Memory Buffer Register.
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The contents of the Memory address (stored in the Memory Address Register) are fetched into the Memory Buffer Register.
  
 
Because it is a LOAD the Memory Buffer Register is copied into the A-reg (Accumulator).
 
Because it is a LOAD the Memory Buffer Register is copied into the A-reg (Accumulator).
  
 
==Execute Transfer Notation (ADD)==
 
==Execute Transfer Notation (ADD)==
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 +
[CIR<sub>operand</sub>] → MAR
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[Memory<sub>mar</sub>] → MBR
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[MBR] + A-reg → A-reg
  
 
===Explanation===
 
===Explanation===
 +
The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.
 +
 +
The contents of the Memory address (stored in the Memory Address Register) are fetched into the Memory Buffer Register.
 +
 +
Because it is a ADD the Memory Buffer Register is added to the current value of the A-reg (Accumulator), and then copied into the A-reg (Accumulator).
  
 
==Execute Transfer Notation (STORE)==
 
==Execute Transfer Notation (STORE)==
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[CIR<sub>operand</sub>] → MAR
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A-reg → MBR
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[MBR] → Memory<sub>mar</sub>
  
 
===Explanation===
 
===Explanation===
 +
The operand from the instruction currently in the Current Instruction Register is copied into the Memory Address Register.
 +
 +
The current value in the A-reg (Accumulator) is copied into the Memory Buffer Register.
 +
 +
The value in the Memory Buffer Register is copied to the memory address (stored in the Memory Address Register) in the Memory.

Latest revision as of 08:15, 23 August 2023

Fetch Decode Execute Cycle

https://www.youtube.com/watch?v=yyHFI5juppA&index=118&list=PLCiOXwirraUDUYF_qDYcZV8Hce8dsE_Ho

TRC Video

https://www.youtube.com/watch?v=PGeNWlz2aaA

Fetch

Fetch Transfer Notation

[PC] → MAR

[Memorymar] → MBR

[PC] + 1 → PC

[MBR] → CIR


Explanation

The address of the next instruction to be executed is copied from the Program Counter to the Memory Address Register.

The instruction at that address (stored in the Memory Address Register) is then copied to the Memory Buffer Register.

Simultaneously, the contents of the Program Counter are incremented by 1.

The contents of the Memory Buffer Register are copied to the Current Instruction Register.

Decode

Decode Transfer Notation

[CIRop-code] → CU

Explanation

The op code from the CIR is passed to the Control Unit

Execute

Execute Transfer Notation (LOAD)

[CIRoperand] → MAR

[Memorymar] → MBR

[MBR] → A-reg

Explanation

The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.

The contents of the Memory address (stored in the Memory Address Register) are fetched into the Memory Buffer Register.

Because it is a LOAD the Memory Buffer Register is copied into the A-reg (Accumulator).

Execute Transfer Notation (ADD)

[CIRoperand] → MAR

[Memorymar] → MBR

[MBR] + A-reg → A-reg

Explanation

The operand of the instruction in the Current Instruction Register is copied into the Memory Address Register.

The contents of the Memory address (stored in the Memory Address Register) are fetched into the Memory Buffer Register.

Because it is a ADD the Memory Buffer Register is added to the current value of the A-reg (Accumulator), and then copied into the A-reg (Accumulator).

Execute Transfer Notation (STORE)

[CIRoperand] → MAR

A-reg → MBR

[MBR] → Memorymar

Explanation

The operand from the instruction currently in the Current Instruction Register is copied into the Memory Address Register.

The current value in the A-reg (Accumulator) is copied into the Memory Buffer Register.

The value in the Memory Buffer Register is copied to the memory address (stored in the Memory Address Register) in the Memory.